1Gb: x4, x8, x16 DDR3 SDRAM
Commands
precharge is not selected, the row will remain open for subsequent accesses. The value
on input A12 (if enabled in the mode register) when the READ command is issued de-
termines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.
Table 72: READ Command Summary
CKE
Prev. Next
BA
A[11,
9:0]
Function
Symbol Cycle Cycle CS# RAS# CAS# WE# [3:0] An
A12 A10
READ
BL8MRS,
BC4MRS
RD
H
L
H
L
H
BA
RFU
V
L
CA
BC4OTF
BL8OTF
RDS4
RDS8
RDAP
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA
BA
BA
RFU
RFU
RFU
L
H
V
L
L
CA
CA
CA
READ with
auto
BL8MRS,
BC4MRS
H
precharge
BC4OTF
BL8OTF
RDAPS4
RDAPS8
H
H
L
L
H
H
L
L
H
H
BA
BA
RFU
RFU
L
H
H
CA
CA
H
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:±] inputs selects the bank. The value on input A1± determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-
mand is issued determines whether BC4 (chop) or BL8 is used.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
Table 73: WRITE Command Summary
CKE
Prev. Next
Symbol Cycle Cycle CS# RAS# CAS# WE# [3:0]
BA
A[11,
9:0]
Function
An
A12 A10
WRITE
BL8MRS,
BC4MRS
WR
H
L
H
L
L
BA
RFU
V
L
CA
BC4OTF
BL8OTF
WRS4
WRS8
WRAP
H
H
H
L
L
L
H
H
H
L
L
L
L
L
L
BA
BA
BA
RFU
RFU
RFU
L
H
V
L
L
CA
CA
CA
WRITE with
auto
BL8MRS,
BC4MRS
H
precharge
BC4OTF
BL8OTF
WRAPS4
WRAPS8
H
H
L
L
H
H
L
L
L
L
BA
BA
RFU
RFU
L
H
H
CA
CA
H
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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120
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