1Gb: x4, x8, x16 DDR3 SDRAM
Commands – Truth Tables
Table 71: Truth Table – CKE
Notes 1–2 apply to the entire table; see Table 70 (page 116) for additional command details
CKE
Previous Cycle4 Present Cycle4
Command5
(RAS#, CAS#, WE#, CS#)
Current State3
(n - 1)
(n)
Action5
Maintain power-down
Power-down exit
Notes
Power-down
L
L
L
“Don’t Care”
DES or NOP
“Don’t Care”
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
REFRESH
H
L
Self refresh
L
Maintain self refresh
Self refresh exit
L
H
L
Bank(s) active
Reading
H
H
H
H
H
H
H
Active power-down entry
Power-down entry
L
Writing
L
Power-down entry
Precharging
Refreshing
All banks idle
L
Power-down entry
L
Precharge power-down entry
Precharge power-down entry
Self refresh
L
6
L
1. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
Notes:
2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.
CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + tCKE (MIN) + tIH.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
previous clock edge.
5. COMMAND is the command registered at the clock edge (must be a legal command as
defined in Table 70 (page 116)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all tim-
ings from previous operations are satisfied. All self refresh exit and power-down exit pa-
rameters are also satisfied.
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