1Gb: x4, x8, x16 DDR3 SDRAM
Commands – Truth Tables
Commands – Truth Tables
Table 70: Truth Table – Command
Notes 1–5 apply to the entire table
CKE
Prev. Next
Symbol Cycle Cycle CS# RAS# CAS# WE# [2:0] An A12 A10
BA
A[11,
9:0] Notes
Function
MODE REGISTER SET
REFRESH
MRS
REF
SRE
SRX
H
H
H
L
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
V
H
L
BA
V
OP code
V
V
V
V
V
V
V
V
Self refresh entry
Self refresh exit
L
L
V
V
V
V
V
6
H
V
H
L
V
H
H
H
H
L
V
6, 7
Single-bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
PRE
PREA
ACT
WR
H
H
H
H
H
H
H
H
BA
V
V
V
V
L
V
V
L
L
H
L
H
L
BA
Row address (RA)
WRITE
BL8MRS,
BC4MRS
H
BA RFU
V
L
CA
8
BC4OTF
BL8OTF
WRS4
WRS8
WRAP
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
L
BA RFU
BA RFU
BA RFU
L
H
V
L
L
CA
CA
CA
8
8
8
WRITE
BL8MRS,
BC4MRS
H
with auto
precharge
BC4OTF
BL8OTF
WRAPS4
WRAPS8
RD
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
L
L
BA RFU
BA RFU
BA RFU
L
H
V
H
H
L
CA
CA
CA
8
8
8
READ
BL8MRS,
BC4MRS
H
BC4OTF
BL8OTF
RDS4
RDS8
RDAP
H
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
BA RFU
BA RFU
BA RFU
L
H
V
L
L
CA
CA
CA
8
8
8
READ
BL8MRS,
BC4MRS
H
with auto
precharge
BC4OTF
BL8OTF
RDAPS4
RDAPS8
NOP
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
X
H
V
H
V
H
H
L
H
H
H
X
H
V
H
V
L
BA RFU
BA RFU
L
H
V
X
V
H
H
V
X
V
CA
CA
V
8
8
L
NO OPERATION
H
X
H
V
H
V
H
H
V
X
V
V
X
V
9
Device DESELECTED
Power-down entry
DES
H
L
X
10
6
PDE
V
H
L
Power-down exit
PDX
L
H
V
V
V
V
V
6, 11
12
H
L
ZQ CALIBRATION LONG
ZQ CALIBRATION SHORT
ZQCL
ZQCS
H
H
H
H
X
X
X
X
X
X
H
L
X
X
L
L
1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising
edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-
dependent.
Notes:
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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