PIC18F2331/2431/4331/4431
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 n 127
n
Operands:
0 f 255
0 b < 7
a [0,1]
Operands:
Operation:
if Overflow bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(f<b>) f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location, ‘f’, is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value.
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Example:
BTG
PORTC,
4
Before Instruction:
PORTC
After Instruction:
PORTC
No
operation
No
operation
No
operation
No
operation
=
0111 0101 [0x75]
0110 0101 [0x65]
If No Jump:
Q1
=
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BOV JUMP
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
If Overflow
PC
2010 Microchip Technology Inc.
DS39616D-page 297
MICROCHIP [ MICROCHIP ]
