PIC18F2331/2431/4331/4431
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 f 255
a [0,1]
Operands:
Operation:
None
000h WDT,
000h WDT postscaler,
1 TO,
Operation:
000h f,
1 Z
1 PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified reg-
ister. If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the post-
scaler of the WDT. Status bits TO and
PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Decode
No
operation
Process
Data
No
operation
Example:
CLRF
FLAG_REG
Example:
CLRWDT
Before Instruction
FLAG_REG
Before Instruction
=
=
0x5A
0x00
WDT Counter
=
?
After Instruction
FLAG_REG
After Instruction
WDT Counter
WDT Postscaler
TO
=
=
=
=
0x00
0
1
1
PD
2010 Microchip Technology Inc.
DS39616D-page 299
MICROCHIP [ MICROCHIP ]
