PIC18F2331/2431/4331/4431
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 n 1023
(PC) + 2 + 2n PC
None
Operands:
0 f 255
0 b 7
a [0,1]
Operation:
1 f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register, ‘f’, is set. If ‘a’ is ‘0’,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
Write to
PC
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
operation
No
operation
No
operation
No
operation
Example:
BSF
FLAG_REG, 7
Example:
HERE
BRA Jump
Before Instruction
FLAG_REG
Before Instruction
=
=
0x0A
0x8A
PC
=
=
address (HERE)
address (Jump)
After Instruction
FLAG_REG
After Instruction
PC
2010 Microchip Technology Inc.
DS39616D-page 295
MICROCHIP [ MICROCHIP ]
