PIC18F2331/2431/4331/4431
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
[ label ] BZ
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 n 127
Operands:
0 k 1048575
s [0,1]
if Zero bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(PC) + 4 TOS,
k PC<20:1>;
if s = 1:
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, the return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs. Then, the
20-bit value, ‘k’, is loaded into
PC<20:1>. CALLis a two-cycle
instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
operation
No
operation
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
Stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
Before Instruction
No
operation
No
operation
No
operation
No
operation
PC
=
address (HERE)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
Example:
HERE
CALL THERE,FAST
address (Jump)
0;
address (HERE + 2)
Before Instruction
PC
After Instruction
=
address (HERE)
PC
=
address (THERE)
TOS
WS
BSRS
STATUSS
=
=
=
=
address (HERE + 4)
W
BSR
STATUS
DS39616D-page 298
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
