PIC18F2331/2431/4331/4431
COMF
Complement f
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) – (W),
Operation:
(f) dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register, ‘f’, are comple-
mented. If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored back in
register, ‘f’. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Description:
Compares the contents of data memory
location, ‘f’, to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
Write to
destination
1(2)
register ‘f’
Note: 3 cycles if skip and followed
by a 2-word instruction.
Example:
COMF
REG, W
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
W
=
=
0x13
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
W
REG
=
=
=
HERE
?
?
After Instruction
If REG
PC
If REG
PC
=
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39616D-page 300
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
