PIC18F2331/2431/4331/4431
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
[ label ] ANDWF
f [,d [,a]]
Syntax:
[ label ] BC
n
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
-128 n 127
if Carry bit is ‘1’,
(PC) + 2 + 2n PC
Operation:
(W) .AND. (f) dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the program
will branch.
Description:
The contents of W are ANDed with
register, ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register, ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
Q1
Q2
Q3
Q4
destination
Decode
Read literal
‘n’
Process
Data
Write to
PC
Example:
ANDWF
REG, W
No
operation
No
operation
No
operation
No
operation
Before Instruction
W
REG
=
=
0x17
0xC2
If No Jump:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read literal
‘n’
Process
Data
No
operation
W
REG
=
=
0x02
0xC2
Example:
HERE
BC JUMP
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
If Carry
PC
2010 Microchip Technology Inc.
DS39616D-page 291
MICROCHIP [ MICROCHIP ]
