PIC17C75X
13.1.3.1 PWM PERIODS
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 and PWM3 outputs can be individually software
configured to use either Timer1 or Timer2 as the
time-base. For PWM2, when TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1, and when TM2PW2 is set, the
time-base is determined by Timer2 and PR2. For
PWM3, when TM2PW3 bit (PW3DCL<5>) is clear, the
time-base is determined by TMR1 and PR1, and when
TM2PW3 is set, the time-base is determined by Timer2
and PR2.
The duty cycle registers for both PWM outputs are dou-
ble buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note: For PW1DCH, PW1DCL, PW2DCH,
PW2DCL, PW3DCH and PW3DCL regis-
ters, a write operation writes to the "master
latches" while a read operation reads the
"slave latches". As a result, the user may
not read back what was just written to the
duty cycle registers.
Running two different PWM outputs on two different
timers allows different PWM periods. Running all
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 can not be used as a 16-bit timer if any PWM is
being used.
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:
ADDWF PW1DCH. This may cause duty cycle outputs
that are unpredictable.
The PWM periods can be calculated as follows:
period of PWM1 = [(PR1) + 1] x 4TOSC
period of PWM2 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
TABLE 13-4: PWM FREQUENCY vs.
RESOLUTION AT 33 MHz
period of PWM3 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
Frequency (kHz)
PWM
Frequency
32.2 64.5 90.66 128.9 515.6
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the
maximum PWM frequency (FPWM) given the value in
the period register.
PRx Value 0xFF 0x7F 0x5A
0x3F
0x0F
6-bit
High
Resolution
10-bit 9-bit 8.5-bit 8-bit
Standard
Resolution
8-bit
7-bit 6.5-bit 6-bit
4-bit
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
13.1.3.2 PWM INTERRUPTS
The PWM modules makes use of the TMR1 and/or
TMR2 interrupts. A timer interrupt is generated when
TMR1 or TMR2 equals its period register and on the
following increment is cleared to zero. This interrupt
also marks the beginning of a PWM cycle. The user
can write new duty cycle values before the timer
roll-over. The TMR1 interrupt is latched into the
TMR1IF bit and the TMR2 interrupt is latched into the
TMR2IF bit. These flags must be cleared in software.
Maximum PWM resolution (bits) for a given PWM fre-
quency:
FOSC
log ( FPWM )
=
bits
log (2)
where: FPWM = 1 / period of PWM
The PWMx duty cycle is as follows:
PWMx Duty Cycle =(DCx) x TOSC
where DCx represents the 10-bit value from
PWxDCH:PWxDCL.
DS30264A-page 98
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
