PIC17C75X
TABLE 13-3: SUMMARY OF TIMER1 AND TIMER2 REGISTERS
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
0000 0000 0000 0000
0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON3
TMR1
TMR2
PIR1
—
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
Timer1’s register
Timer2’s register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TX1IF
TX1IE
T0IE
RC1IF
RC1IE
INTE
PIE1
TMR3IE TMR2IE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
—
T0IF
T0CKIE
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 1100 --11 qq11
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
PR1
Timer1 period register
Timer2 period register
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
DC1
DC1
DC1
DC9
DC9
DC9
DC0
DC0
DC0
DC8
DC8
DC8
—
TM2PW2
TM2PW3
DC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC6
DC5
DC5
DC5
DC4
DC4
DC4
DC3
DC3
DC3
DC2
DC2
DC2
DC7
DC7
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
DS30264A-page 96
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
