29. Register Summary (Continued)
Address
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
(0xBE)
(0xBD)
(0xBC)(5)
(0xBB)(5)
(0xBA)(5)
Name
CANEN2
CANGIE
CANGIT
CANGSTA
CANGCON
Reserved
Reserved
Reserved
Reserved
Reserved
LINDAT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ENMOB2
ENBX
CERG
ENFG
TEST
–
Bit 1
ENMOB1
ENERG
FERG
BOFF
ENA/STB
–
Bit 0
ENMOB0
ENOVRT
AERG
ERRP
SWRES
–
Page
162
161
160
159
158
–
–
ENMOB5
ENMOB4
ENMOB3
ENIT
ENBOFF
ENRX
ENTX
ENERR
CANIT
BOFFIT
OVRTIM
BXOK
SERG
–
OVRG
–
TXBSY
RXBSY
ABRQ
OVRQ
TTC
SYNTTC
LISTEN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LDATA5
–
–
LDATA4
–
–
–
–
–
LDATA7
LDATA6
LDATA3
LDATA2
LINDX2
LID2
LDATA1
LINDX1
LID1
LDATA0
LINDX0
LID0
196
196
195
195
194
194
194
193
193
192
191
LINSEL
–
–
/LAINC
LINIDR
LP1
LP0
LID5 / LDL1 LID4 / LDL0
LID3
LINDLR
LINBRRH
LINBRRL
LINBTR
LINERR
LINENIR
LINSIR
LTXDL3
LTXDL2
LTXDL1
LTXDL0
LRXDL3
LRXDL2
LDIV10
LDIV2
LBT2
LPERR
LRXDL1
LDIV9
LDIV1
LBT1
LCERR
LRXDL0
LDIV8
LDIV0
LBT0
LBERR
–
–
–
–
LDIV11
LDIV7
LDIV6
LDIV5
LDIV4
LDIV3
LDISR
–
LBT5
LBT4
LBT3
LABORT
LTOERR
LOVERR
LFERR
LSERR
–
–
–
–
LENERR
LENIDOK LENTXOK LENRXOK
LIDST2
LIDST1
LIDST0
LBUSY
LERR
LIDOK
LTXOK
LRXOK
LINCR
LSWRES
LIN13
LCONF1
LCONF0
LENA
LCMD2
LCMD1
LCMD0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PIFR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PEV2
PEVE2
PAOC2
PEV1
PEVE1
PRFM22
PEV0
PEVE0
PRFM21
PEOP
PEOPE
PRFM20
132
132
131
PIM
PMIC2
POVEN2
PISEL2
PELEV2
PFLTE2
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
300
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
