28. Instruction Set Summary (Continued)
Mnemonics
SET
Operands
Description
Set T in SREG
Operation
T 1
Flags
#Clocks
T
T
1
1
1
1
CLT
Clear T in SREG
T 0
SEH
Set half carry flag in SREG
Clear half carry flag in SREG
H 1
H
H
CLH
H 0
Data Transfer Instructions
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move between registers
Copy register word
Rd Rr
Rd+1:Rd Rr+1:Rr
Rd K
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Load immediate
Rd, X
Load indirect
Rd (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load indirect and post-inc.
Load indirect and pre-dec.
Load indirect
Rd (X), X X + 1
X X - 1, Rd (X)
Rd (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load indirect and post-inc.
Load indirect and pre-dec.
Load indirect with displacement
Load indirect
Rd (Y), Y Y + 1
Y Y –1, Rd (Y)
Rd (Y + q)
Rd (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load indirect and post-inc.
Load indirect and pre-dec.
Load indirect with displacement
Load direct from SRAM
Store indirect
Rd (Z), Z Z+1
Z Z – 1, Rd (Z)
Rd (Z + q)
Rd (k)
LD
LDD
LDS
ST
X, Rr
(X) Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store indirect and post-inc.
Store indirect and pre-dec.
Store indirect
(X) Rr, X X + 1
X X – 1, (X) Rr
(Y) Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store indirect and post-inc.
Store indirect and pre-dec.
Store indirect with displacement
Store indirect
(Y) Rr, Y Y + 1
Y Y - 1, (Y) Rr
(Y + q) Rr
ST
STD
ST
(Z) Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store indirect and post-inc.
Store indirect and pre-dec.
Store indirect with displacement
Store direct to SRAM
Load program memory
Load program memory
Load program memory and post-inc
Store program memory
In port
(Z) Rr, Z Z + 1
Z Z - 1, (Z) Rr
(Z + q) Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) Rr
R0 (Z)
Rd, Z
Rd (Z)
Rd, Z+
Rd (Z), Z Z+1
(Z) R1:R0
Rd, P
P, Rr
Rr
Rd P
1
1
2
2
OUT
PUSH
POP
Out port
P Rr
Push register on stack
Pop register from stack
STACK Rr
Rd STACK
Rd
MCU Control Instructions
NOP
SLEEP
WDR
No operation
Sleep
None
None
None
None
1
1
(see specific descr. for sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog reset
Break
1
BREAK
N/A
Note:
1. These Instructions are only available in “16K and 32K parts”
298
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
