29. Register Summary (Continued)
Address
Name
SMCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
34
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
–
–
–
–
SM2
SM1
SM0
SE
MSMCR
MONDR
ACSR
Monitor Stop Mode Control Register
Monitor Data Register
Reserved
Reserved
231
AC3IF
–
AC2IF
–
AC1IF
AC0IF
AC3O
AC2O
AC1O
–
AC0O
–
Reserved
SPDR
–
–
–
–
SPD2
–
SPD7
SPIF
SPIE
–
SPD6
WCOL
SPE
SPD5
SPD4
SPD3
SPD1
–
SPD0
SPI2X
SPR0
–
139
139
138
SPSR
–
–
–
SPCR
DORD
MSTR
CPOL
CPHA
–
SPR1
–
Reserved
Reserved
PLLCSR
OCR0B
OCR0A
TCNT0
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
EEDR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
OCR0B5
OCR0A5
TCNT05
–
–
OCR0B4
OCR0A4
TCNT04
–
–
PLLF
OCR0B2
OCR0A2
TCNT02
CS02
–
PLLE
OCR0B1
OCR0A1
TCNT01
CS01
WGM01
–
PLOCK
OCR0B0
OCR0A0
TCNT00
CS00
WGM00
PSRSYNC
EEAR8
EEAR0
EEDR0
EERE
GPIOR00
INT0
31
90
90
90
89
86
76
20
20
20
21
24
71
72
73
24
24
OCR0B7
OCR0A7
TCNT07
FOC0A
COM0A1
TSM
OCR0B6
OCR0A6
TCNT06
FOC0B
COM0A0
ICPSEL1
–
OCR0B3
OCR0A3
TCNT03
WGM02
COM0B1
–
COM0B0
–
–
–
–
–
–
–
–
–
EEAR9
EEAR1
EEDR1
EEWE
GPIOR01
INT1
INTF1
PCIF1
GPIOR21
GPIOR11
–
EEAR7
EEDR7
–
EEAR6
EEDR6
–
EEAR5
EEDR5
–
EEAR4
EEDR4
–
EEAR3
EEAR2
EEDR2
EEMWE
GPIOR02
INT2
INTF2
PCIF2
GPIOR22
GPIOR12
–
EEDR3
EECR
EERIE
GPIOR0
EIMSK
GPIOR07 GPIOR06 GPIOR05 GPIOR04
GPIOR03
–
–
–
–
–
–
–
–
–
–
–
–
INT3
EIFR
INTF3
INTF0
PCIF0
GPIOR20
GPIOR10
–
PCIFR
PCIF3
GPIOR2
GPIOR1
Reserved
Reserved
TIFR1
GPIOR27 GPIOR26 GPIOR25 GPIOR24
GPIOR17 GPIOR16 GPIOR15 GPIOR14
GPIOR23
GPIOR13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ICF1
OCF1B
OCF0B
–
OCF1A
OCF0A
–
TOV1
TOV0
–
115
91
TIFR0
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
–
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
304
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
