29. Register Summary (Continued)
Address
(0x76)
Name
AMP1CSR
AMP0CSR
Reserved
Reserved
Reserved
Reserved
Reserved
TIMSK1
TIMSK0
PCMSK3
PCMSK2
PCMSK1
PCMSK0
EICRA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
219
AMP1EN
AMP1IS
AMP1G1
AMP1G0
AMPCMP1 AMP1TS2 AMP1TS1 AMP1TS0
AMPCMP0 AMP0TS2 AMP0TS1 AMP0TS0
(0x75)
AMP0EN
AMP0IS
AMP0G1
AMP0G0
218
(0x74)
–
–
–
–
–
–
–
–
(0x73)
–
–
–
–
–
–
–
–
(0x72)
–
–
–
–
–
–
–
–
(0x71)
–
–
–
–
–
–
–
–
–
–
(0x70)
–
–
–
–
–
–
(0x6F)
–
–
ICIE1
–
–
OCIE1B
OCIE1A
OCIE0A
PCINT25
PCINT17
PCINT9
PCINT1
ISC01
PCIE1
–
TOIE1
TOIE0
PCINT24
PCINT16
PCINT8
PCINT0
ISC00
PCIE0
–
114
90
73
73
74
74
71
72
(0x6E)
(0x6D)
(0x6C)
(0x6B)
(0x6A)
(0x69)
–
–
–
–
–
OCIE0B
–
–
–
–
–
PCINT26
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
(0x68)
PCICR
–
–
–
–
PCIE3
PCIE2
(0x67)
Reserved
OSCCAL
Reserved
PRR
–
–
–
–
–
–
(0x66)
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
–
CAL0
–
29
36
(0x65)
–
–
–
–
–
–
(0x64)
–
PRCAN
PRPSC
PRTIM1
PRTIM0
PRSPI
PRLIN
–
PRADC
–
(0x63)
Reserved
Reserved
CLKPR
–
–
–
–
–
–
(0x62)
–
–
–
–
–
–
–
–
(0x61)
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
WDP1
Z
CLKPS0
WDP0
C
33
45
12
15
15
(0x60)
WDTCSR
SREG
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
I
T
H
S
V
N
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP0
–
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
0x3C (0x5C) Reserved
–
–
–
–
–
–
–
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SPMIE
–
–
–
–
–
BLBSET
–
–
PGWRT
–
–
–
RWWSB
SIGRD
RWWSRE
PGERS
–
SPMEN
–
244
–
–
–
–
–
–
–
PUD
–
SPIPS
–
–
–
IVSEL
EXTRF
IVCE
PORF
50, 57
42
MCUSR
WDRF
BORF
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
ATmega16/32/64/M1/C1 [DATASHEET]
303
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
