29. Register Summary
Address
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Reserved
Reserved
Reserved
Reserved
Reserved
CANMSG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MSG 7
MSG 6
MSG 5
MSG 4
MSG 3
MSG 2
MSG 1
MSG 0
171
171
171
170
170
170
170
169
169
169
169
168
167
166
166
166
165
165
165
165
165
165
164
163
163
163
163
162
162
162
CANSTMPH TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8
CANSTMPL TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4
TIMSTM3
IDMSK24
IDMSK16
TIMSTM2
IDMSK23
IDMSK15
TIMSTM1 TIMSTM0
CANIDM1
CANIDM2
CANIDM3
CANIDM4
CANIDT1
CANIDT2
CANIDT3
CANIDT4
IDMSK28
IDMSK20
IDMSK12
IDMSK27
IDMSK19
IDMSK11
IDMSK26
IDMSK18
IDMSK10
IDMSK25
IDMSK17
IDMSK22
IDMSK14
IDMSK21
IDMSK13
IDMSK
9
1
IDMSK
8
0
IDMSK
7
IDMSK
6
IDMSK5
IDMSK
4
IDMSK
3
IDMSK
2
IDMSK
IDMSK
RTRMSK
IDT23
–
IDEMSK
IDT21
IDT28
IDT20
IDT12
IDT27
IDT19
IDT11
IDT26
IDT18
IDT10
IDT25
IDT17
IDT24
IDT16
IDT22
IDT14
IDT15
IDT13
IDT
9
1
IDT
8
0
IDT7
IDT6
IDT5
IDT4
IDT3
IDT2
IDT
IDT
RTRTAG
DLC2
RB1TAG
DLC1
RB0TAG
DLC0
CANCDMOB CONMOB1 CONMOB0
RPLV
IDE
BERR
DLC3
SERR
AINC
CANSTMOB
CANPAGE
DLCW
TXOK
RXOK
CERR
INDX2
CGP2
REC2
TEC2
FERR
AERR
MOBNB3 MOBNB2 MOBNB1
MOBNB0
HPMOB0
REC4
INDX1
CGP1
INDX0
CGP0
CANHPMOB HPMOB3 HPMOB2 HPMOB1
CGP3
REC3
TEC3
CANREC
CANTEC
REC7
TEC7
REC6
TEC6
REC5
TEC5
REC1
REC0
TEC4
TEC1
TEC0
CANTTCH TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10
CANTTCL TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2
TIMTTC9
TIMTTC1
TIMTTC8
TIMTTC0
CANTIMH CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8
CANTIML
CANTCON
CANBT3
CANBT2
CANBT1
CANSIT1
CANSIT2
CANIE1
CANTIM7 CANTIM6 CANTIM5 CANTIM4
CANTIM3
TPRSC3
PHS12
PRS2
BRP2
–
CANTIM2
TPRSC2
PHS11
PRS1
BRP1
–
CANTIM1 CANTIM0
TPRSC7
TPRSC6
TPRSC5
PHS21
SJW0
BRP4
–
TPRSC4
TRPSC1
PHS10
PRS0
BRP0
–
TPRSC0
–
–
–
–
–
–
–
–
PHS22
PHS20
SMP
SJW1
–
–
BRP5
BRP3
–
–
–
–
–
–
–
–
SIT5
–
SIT4
SIT3
SIT2
SIT1
–
SIT0
–
IEMOB4
–
–
–
–
IEMOB0
–
CANIE2
IEMOB5
–
IEMOB3
–
IEMOB2
–
IEMOB1
–
CANEN1
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
ATmega16/32/64/M1/C1 [DATASHEET]
299
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
