28. Instruction Set Summary (Continued)
Mnemonics
SBIS
Operands
Description
Skip if bit in I/O register is set
Branch if status flag Set
Branch if status flag cleared
Branch if equal
Operation
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1/2/3
1/2
P, b
s, k
s, k
k
if (P(b)=1) PC PC + 2 or 3
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
if (SREG(s) = 1) then PC PC + k + 1
if (SREG(s) = 0) then PC PC + k + 1
if (Z = 1) then PC PC + k + 1
if (Z = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (C = 1) then PC PC + k + 1
if (N = 1) then PC PC + k + 1
if (N = 0) then PC PC + k + 1
if (N V= 0) then PC PC + k + 1
if (N V= 1) then PC PC + k + 1
if (H = 1) then PC PC + k + 1
if (H = 0) then PC PC + k + 1
if (T = 1) then PC PC + k + 1
if (T = 0) then PC PC + k + 1
if (V = 1) then PC PC + k + 1
if (V = 0) then PC PC + k + 1
if (I = 1) then PC PC + k + 1
if (I = 0) then PC PC + k + 1
1/2
1/2
k
Branch if not equal
1/2
k
Branch if carry set
1/2
k
Branch if carry cleared
Branch if same or higher
Branch if lower
1/2
k
1/2
k
1/2
k
Branch if minus
1/2
BRPL
BRGE
BRLT
k
Branch if plus
1/2
k
Branch if greater or equal, signed
Branch if less than zero, signed
Branch if half carry flag set
Branch if half carry flag cleared
Branch if T flag set
1/2
k
1/2
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
1/2
k
1/2
k
1/2
k
Branch if T flag cleared
Branch if overflow flag is set
Branch if overflow flag is cleared
Branch if interrupt enabled
Branch if interrupt disabled
1/2
k
1/2
k
1/2
k
1/2
BRID
k
1/2
Bit and Bit-test Instructions
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set bit in I/O register
Clear bit in I/O register
Logical shift left
I/O(P,b) 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O(P,b) 0
None
LSL
Rd(n+1) Rd(n), Rd(0) 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical shift right
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
Rotate left through carry
Rotate right through carry
Arithmetic shift right
Swap nibbles
Rd(0) C,Rd(n+1) Rd(n), C Rd(7)
Z,C,N,V
Rd(7) C,Rd(n) Rd(n+1), C Rd(0)
Z,C,N,V
Rd(n) Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0)
None
Flag set
SREG(s) 1
SREG(s) 0
T Rr(b)
Rd(b) T
C 1
SREG(s)
s
Flag clear
SREG(s)
Rr, b
Rd, b
Bit store from register to T
Bit load from T to register
Set carry
T
None
C
Clear carry
C 0
C
Set negative flag
N 1
N
Clear negative flag
Set zero flag
N 0
N
Z 1
Z
Clear zero flag
Z 0
Z
Global interrupt enable
Global interrupt disable
Set signed test flag
Clear signed test flag
Set twos complement overflow.
Clear twos complement overflow
I 1
I
CLI
I 0
I
SES
CLS
SEV
CLV
S 1
S
S 0
S
V 1
V
V 0
V
Note:
1. These Instructions are only available in “16K and 32K parts”
ATmega16/32/64/M1/C1 [DATASHEET]
297
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
