29. Register Summary (Continued)
Address
(0x96)
(0x95)
(0x94)
(0x93)
Name
Bit 7
AC2EN
AC1EN
AC0EN
–
Bit 6
AC2IE
AC1IE
AC0IE
–
Bit 5
AC2IS1
AC1IS1
AC0IS1
–
Bit 4
AC2IS0
AC1IS0
AC0IS0
–
Bit 3
Bit 2
AC2M2
AC1M2
AC0M2
–
Bit 1
AC2M1
AC1M1
AC0M1
–
Bit 0
AC2M0
AC1M0
AC0M0
–
Page
229
AC2CON
AC1CON
AC0CON
Reserved
–
AC1ICE
ACCKSEL
–
228
227
DAC9 /
DAC3
DAC8 /
DAC2
(0x92)
(0x91)
DACH
DACL
- / DAC9
- / DAC8
- / DAC7
DAC5 / -
- / DAC6
DAC4 / -
- / DAC5
DAC3 / -
- / DAC4
DAC2 / -
235
DAC7 /
DAC1
DAC6
/DAC0
DAC1 / -
DAC0 /
235
234
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
(0x7C)
(0x7B)
(0x7A)
DACON
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
DAATE
DATS2
DATS1
DATS0
–
–
–
–
–
DALA
–
DAOE
–
DAEN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11
OCR1B7 OCR1B6 OCR1B5 OCR1B4 OCR1B3
OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
ICR12
TCNT110
TCNT12
–
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
ICR11
TCNT19
TCNT11
–
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
ICR10
TCNT18
TCNT10
–
113
113
113
113
114
114
113
113
OCR1A7
ICR115
ICR17
OCR1A6
ICR114
ICR16
OCR1A5
ICR113
ICR15
OCR1A4
ICR112
ICR14
OCR1A3
ICR111
ICR13
TCNT111
TCNT13
–
ICR1L
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
TCNT115 TCNT114 TCNT113 TCNT112
TCNT17
–
TCNT16
–
TCNT15
–
TCNT14
–
FOC1A
ICNC1
COM1A1
–
FOC1B
ICES1
COM1A0
AMP2PD
ADC6D
–
–
–
WGM13
COM1B0
AMP0PD
ADC4D
–
–
–
–
–
113
112
110
214
214
–
WGM12
–
CS12
–
CS11
WGM11
ADC9D
ADC1D
–
CS10
WGM10
ADC8D
ADC0D
–
COM1B1
ACMP0D
ADC5D
–
AMP0ND
ADC3D
–
ADC10D
ADC2D
–
DIDR0
ADC7D
–
Reserved
ADMUX
ADCSRB
ADCSRA
REFS1
ADHSM
ADEN
REFS0
ISRCEN
ADSC
ADLAR
AREFEN
ADATE
–
MUX3
ADTS3
ADIE
MUX2
ADTS2
ADPS2
MUX1
ADTS1
ADPS1
MUX0
ADTS0
ADPS0
33
–
212
211
ADIF
ADC9 /
ADC3
ADC8 /
ADC2
(0x79)
ADCH
- / ADC9
- / ADC8
- / ADC7
- / ADC6
- / ADC5
ADC3 / -
- / ADC4
ADC2 / -
213
ADC7 /
ADC1
ADC6 /
ADC0
(0x78)
(0x77)
ADCL
ADC5 / -
AMP2G1
ADC4 / -
AMP2G0
ADC1 / -
ADC0 /
213
219
AMP2CSR
AMP2EN
AMP2IS
AMPCMP2 AMP2TS2 AMP2TS1 AMP2TS0
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
302
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
