29. Register Summary (Continued)
Address
(0xB9)(5)
(0xB8)(5)
(0xB7)(5)
(0xB6)(5)
(0xB5)(5)
(0xB4)(5)
(0xB3)(5)
(0xB2)(5)
(0xB1)(5)
(0xB0)(5)
(0xAF)(5)
(0xAE)(5)
(0xAD)(5)
(0xAC)(5)
(0xAB)(5)
(0xAA)(5)
(0xA9)(5)
(0xA8)(5)
(0xA7)(5)
(0xA6)(5)
(0xA5)(5)
(0xA4)(5)
(0xA3)(5)
(0xA2)(5)
(0xA1)(5)
(0xA0)(5)
(0x9F)
Name
PMIC1
PMIC0
PCTL
Bit 7
Bit 6
Bit 5
Bit 4
PFLTE1
PFLTE0
–
Bit 3
PAOC1
PAOC0
–
Bit 2
PRFM12
PRFM02
–
Bit 1
PRFM11
PRFM01
PCCYC
POEN0B
–
Bit 0
PRFM10
PRFM00
PRUN
POEN0A
–
Page
131
131
130
33
POVEN1
PISEL1
PELEV1
PELEV0
PCLKSEL
POEN2B
PULOCK
POVEN0
PISEL0
PPRE1
PPRE0
POC
–
–
–
–
–
–
–
–
POEN2A
PMODE
POEN1B
POPB
POEN1A
POPA
PCNF
130
128
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
PSYNC
POCR_RBH
PSYNC21 PSYNC20 PSYNC11
PSYNC10 PSYNC01 PSYNC00
–
–
POCR_RB11 POCR_RB10 POCR_RB9 POCR_RB8
POCR_RBL POCR_RB7 POCR_RB6 POCR_RB5 POCR_RB4 POCR_RB3 POCR_RB2 POCR_RB1 POCR_RB0
POCR2SBH POCR2SB11 POCR2SB10 POCR2SB9 POCR2SB8
POCR2SBL POCR2SB7 POCR2SB6 POCR2SB5 POCR2SB4 POCR2SB3 POCR2SB2 POCR2SB1 POCR2SB0
POCR2RAH POCR2RA11 POCR2RA10 POCR2RA9 POCR2RA8
POCR2RAL POCR2RA7 POCR2RA6 POCR2RA5 POCR2RA4 POCR2RA3 POCR2RA2 POCR2RA1 POCR2RA0
POCR2SAH POCR2SA11 POCR2SA10 POCR2SA9 POCR2SA8
POCR2SAL POCR2SA7 POCR2SA6 POCR2SA5 POCR2SA4 POCR2SA3 POCR2SA2 POCR2SA1 POCR2SA0
POCR1SBH POCR1SB11 POCR1SB10 POCR1SB9 POCR1SB8
POCR1SBL POCR1SB7 POCR1SB6 POCR1SB5 POCR1SB4 POCR1SB3 POCR1SB2 POCR1SB1 POCR1SB0
POCR1RAH POCR1RA11 POCR1RA10 POCR1RA9 POCR1RA8
POCR1RAL POCR1RA7 POCR1RA6 POCR1RA5 POCR1RA4 POCR1RA3 POCR1RA2 POCR1RA1 POCR1RA0
POCR1SAH POCR1SA11 POCR1SA10 POCR1SA9 POCR1SA8
POCR1SAL POCR1SA7 POCR1SA6 POCR1SA5 POCR1SA4 POCR1SA3 POCR1SA2 POCR1SA1 POCR1SA0
POCR0SBH POCR0SB11 POCR0SB10 POCR0SB9 POCR0SB8
POCR0SBL POCR0SB7 POCR0SB6 POCR0SB5 POCR0SB4 POCR0SB3 POCR0SB2 POCR0SB1 POCR0SB0
POCR0RAH POCR0RA11 POCR0RA10 POCR0RA9 POCR0RA8
POCR0RAL POCR0RA7 POCR0RA6 POCR0RA5 POCR0RA4 POCR0RA3 POCR0RA2 POCR0RA1 POCR0RA0
POCR0SAH POCR0SA11 POCR0SA10 POCR0SA9 POCR0SA8
POCR0SAL POCR0SA7 POCR0SA6 POCR0SA5 POCR0SA4 POCR0SA3 POCR0SA2 POCR0SA1 POCR0SA0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AC3CON
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x9E)
–
–
–
–
–
–
–
(0x9D)
–
–
–
–
–
–
–
(0x9C)
–
–
–
–
–
–
–
(0x9B)
–
–
–
–
–
–
–
(0x9A)
–
–
–
–
–
–
–
(0x99)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(0x98)
(0x97)
AC3EN
AC3IE
AC3IS1
AC3IS0
AC3M2
AC3M1
AC3M0
229
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations
are reserved.
ATmega16/32/64/M1/C1 [DATASHEET]
301
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
