AT25128B/AT25256B
Device Operation
Figure 5-2.ꢀHold Mode
CS
SCK
HOLD
Hold
Hold
Hold
Figure 5-3.ꢀHold Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
5.4
Write Protection
The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin
is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The
WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS
register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will
allow the user to install the AT25128B/AT25256B device in a system with the WP pin tied to ground and
still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to
a logic ‘1’.
DS20006193A-page 17
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