AT25128B/AT25256B
Device Operation
5.
Device Operation
The AT25128B/AT25256B is controlled by a set of instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI Master communicates with the AT25128B/AT25256B
via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial
Data Input (SI), and Serial Data Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI
bus. The AT25128B/AT25256B supports the two most common modes, SPI Modes 0 and 3. With SPI
Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the
inactive state (when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is
defined as a low SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive
state. The SCK Idle state must match when the CS is deasserted both before and after the
communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid
line on SCK while CS is inactive and Mode 3 with a dotted line.
Figure 5-1.ꢀSPI Mode 0 and Mode 3
CS
Mode 3
Mode 0
Mode 3
Mode 0
SCK
SI
MSB
LSB
MSB
LSB
SO
5.1
Interfacing the AT25128B/AT25256B on the SPI Bus
Communication to and from the AT25128B/AT25256B must be initiated by the SPI Master device, such
as a microcontroller. The SPI Master device must generate the serial clock for the AT25128B/AT25256B
on the Serial Data Clock (SCK) pin. The AT25128B/AT25256B always operates as a slave due to the fact
that the SCK is always an input.
5.1.1
5.1.2
Selecting the Device
The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin
will remain in a high‑impedance state.
Sending Data to the Device
The AT25128B/AT25256B uses the SI pin to receive information. All instructions, addresses and data
input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the
first rising edge of the SCK line after the CS has been asserted.
DS20006193A-page 15
© 2019 Microchip Technology Inc.
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