AT25128B/AT25256B
Device Commands and Addressing
6.
Device Commands and Addressing
The AT25128B/AT25256B is designed to interface directly with the synchronous Serial Peripheral
Interface (SPI). The AT25128B/AT25256B utilizes an 8‑bit instruction register. The list of instructions and
their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with
the MSb first and start with a high‑to‑low CS transition.
Table 6-1.ꢀInstruction Set for the AT25128B/AT25256B
Instruction Name
WREN
Instruction Format Operates On
Operation Description
Set Write Enable Latch (WEL)
Reset Write Enable Latch (WEL)
Read STATUS Register
Write STATUS Register
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
STATUS Register
STATUS Register
STATUS Register
STATUS Register
Memory Array
WRDI
RDSR
WRSR
READ
Read from Memory Array
Write to Memory Array
WRITE
Memory Array
6.1
STATUS Register Bit Definition and Function
The AT25128B/AT25256B includes an 8‑bit STATUS register. The STATUS register bits modulate various
features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific
instructions that are detailed in the following sections.
Table 6-2.ꢀSTATUS Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEL
RDY/BSY
Table 6-3.ꢀSTATUS Register Bit Definition
Bit
Name
Type
Description
0
1
0
7
WPEN Write-Protect Enable
R/W
See Table 6-5 (Factory Default)
See Table 6-5 (Factory Default)
6:4
3:2
RFU
Reserved for Future Use
Block Write Protection
R
Reads as zeros when the device is not in a write
cycle
1
00
01
10
11
0
Reads as ones when the device is in a write cycle
No array write protection (Factory Default)
Quarter array write protection (see Table 6-4)
Half array write protection (see Table 6-4)
Entire array write protection (see Table 6-4)
Device is not write enabled (Power-up Default)
Device is write enabled
BP1
BP0
R/W
1
WEL
Write Enable Latch
R/W
1
DS20006193A-page 18
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