AT25128B/AT25256B
Device Commands and Addressing
Figure 6-2.ꢀWREN Timing
CS
0
1
2
3
4
5
6
7
SCK
SI
WREN Opcode (06h)
0
0
0
0
0
1
1
0
MSB
High-Impedance
SO
6.3.2
Write Disable Instruction (WRDI)
To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h)
disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDIinstruction is independent
of the status of the WP pin.
Figure 6-3.ꢀWRDI Timing
CS
0
1
2
3
4
5
6
7
SCK
SI
WRDI Opcode (04h)
0
0
0
0
0
1
0
0
MSB
High-Impedance
SO
6.4
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the
STATUS register. Before a WRSRinstruction can be initiated, a WRENinstruction must be executed to set
the WEL to logic ‘1’. Upon completion of a WRENinstruction, a WRSRinstruction can be executed.
Note:ꢀ The WRSRinstruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only
bit 7, bit 3 and bit 2 can be changed via the WRSRinstruction. These modifiable bits are the Write Protect
Enable (WPEN) and Block Protect (BP<1:0>) bits. These three bits are nonvolatile bits that have the
same properties and functions as regular EEPROM cells. Their values are retained while power is
removed from the device.
DS20006193A-page 20
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