AT25128B/AT25256B
Device Commands and Addressing
...........continued
Bit
Name
Type
Description
Device is ready for a new sequence
0
1
0
RDY/BSY Ready/Busy Status
R
Device is busy with an internal operation
6.2
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy
and write enable status of the device can be determined by the RDSRinstruction. Similarly, the Block
Write Protection (BP<1:0>) bits indicate the extent of memory array protection employed. The STATUS
register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon
completion of the opcode, the device will return the 8‑bit STATUS register value on the SO pin.
Figure 6-1.ꢀRDSR Waveform
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
RDSR Opcode (05h)
0
0
0
0
0
1
0
1
MSB
STATUS Register Data Out
High-Impedance
SO
D7
D6
D5 D4
D3 D2
D1
D0
MSB
6.3
Write Enable (WREN) and Write Disable (WRDI)
Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the
Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the
status of the WEL bit in the STATUS register.
6.3.1
Write Enable Instruction (WREN)
The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write
STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by
sending a WREN(06h) instruction to the AT25128B/AT25256B. First, the CS pin is driven low to select the
device and then a WRENinstruction is clocked in on the SI pin. Then the CS pin can be driven high and
the WEL bit will be updated in the STATUS register to a logic ‘1’. The device will power‑up in the write
disable state (WEL = 0).
DS20006193A-page 19
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