AT25128B/AT25256B
Device Commands and Addressing
The AT25128B/AT25256B will not respond to commands other than a RDSRafter a WRSRinstruction until
the self-timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the
STATUS register is reset to logic ‘0’.
Figure 6-4.ꢀWRSR Waveform
(1)
CS
tWC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
STATUS Register Data In
WRSR Opcode (01h)
0
0
0
0
0
0
0
1
D7
X
X
X
D3
D2
X
X
MSB
MSB
High-Impedance
SO
Note:ꢀ
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
6.4.1
Block Write-Protect Function
The WRSRinstruction allows the user to select one of four possible combinations as to how the memory
array will be inhibited from writing through changing the Block Write-Protect bits (BP<1:0>). The four
levels of array protection are:
• None of the memory array is protected.
• Upper quarter (¼) address range is write-protected meaning the highest order address bits are read-
only.
• Upper half (½) address range is write-protected meaning the highest order address bits are read-
only.
• All of the memory array is write-protected meaning all address bits are read-only.
The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.
Table 6-4.ꢀBlock Write-Protect Bits
Level
STATUS Register Bits
Write-Protected/Read‑Only Address Range
BP1
0
BP0
0
AT25128B
None
AT25256B
None
0
0
1
1(1/4)
2(1/2)
3(All)
3000h-3FFFh
2000h-3FFFh
0000h-3FFFh
6000h-7FFFh
4000h – 7FFFh
0000h – 7FFFh
1
0
1
1
DS20006193A-page 21
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