AT25128B/AT25256B
Electrical Characteristics
4.6.2
Pin Capacitance
Table 4-5.ꢀPin Capacitance(1,2)
Symbol Test Condition
Max. Units Conditions
COUT
CIN
Output Capacitance (SO)
8
6
pF
pF
VOUT = 0V
VIN = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
Note:ꢀ
1. This parameter is characterized but is not 100% tested in production.
2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V
(unless otherwise noted).
4.6.3
EEPROM Cell Performance Characteristics
Table 4-6.ꢀEEPROM Cell Performance Characteristics
Operation
Test Condition
Min.
Max.
Units
Write Endurance(1)
TA = 25°C, VCC = 3.3V,
Page Write mode
1,000,000
—
Write Cycles
Data Retention(1)
TA = 55°C
100
—
Years
Note:ꢀ
1. Performance is determined through characterization and the qualification process.
4.6.4
4.6.5
Software Reset
The SPI interface of the AT25128B/AT25256B can be reset by toggling the CS input. If the CS line is
already in the active state, it must complete a transition from the inactive state (≥VIH) to the active state
(≤VIL) and then back to the inactive state (≥VIH) without sending clocks on the SCK line. Upon completion
of this sequence, the device will be ready to receive a new opcode on the SI line.
Device Default State at Power-Up
The AT25128B/AT25256B default state upon power-up consists of:
• Standby Power mode
• A high-to-low-level transition on CS is required to enter active state
• Write Enable Latch (WEL) bit in the STATUS register = 0
• Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command
• Device is not selected
• Not in Hold condition
• WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the
fact that they are nonvolatile values
4.6.6
Device Default Condition
The AT25128B/AT25256B is shipped from Microchip to the customer with the EEPROM array set to an all
FFh data pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0’
(the ability of the EEPROM array to write is dictated by the values of the Block Write‑Protect bits while the
STATUS register’s ability to write is controlled by the WEL bit). The Block Write Protection bits in the
STATUS register are set to logic ‘0’ (no write protection selected).
DS20006193A-page 14
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