AT25128B/AT25256B
Device Operation
5.1.3
Receiving Data from the Device
Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is
latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the
Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See Read Sequence
for more details.
5.2
Device Opcodes
5.2.1
Serial Opcode
After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte
contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes
that the AT25128B/AT25256B will respond to.
5.2.2
Invalid Opcode
If an invalid opcode is received, no data will be shifted into AT25128B/AT25256B and the SO pin will
remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the
serial communication.
5.3
Hold Function
The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without
having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the
internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the
operation and the write cycle will continue to completion.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by
asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse,
then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will
remain in the Hold mode as long as the HOLD pin and CS pin are asserted.
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the
SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in
the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the
SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end
until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been
started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’
state.
DS20006193A-page 16
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