W3H128M72E-XSBX / W3H128M72E-XNBX
where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might
not be intuitive, they have also been included. Upon completion of
a burst, assuming no other commands have been initiated, the DQ
will remain High-Z and any additional input data will be ignored.
WRITE COMMAND
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–9 selects the starting
column location. The value on input A10 determines whether or
not auto precharge is used. If auto precharge is selected, the
row being accessed will be precharged at the end of the WRITE
burst; if auto precharge is not selected, the row will remain open
for subsequent accesses.
Data for any WRITE burst may be concatenated with a subsequent
WRITE command to provide continuous flow of input data. The first
data element from the new burst is applied after the last element
of a completed burst. The new WRITE command should be issued
x cycles after the first WRITE command, where x equals BL/2.
DDR2 SDRAM supports concurrent auto precharge options, as
shown in Table 4.
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying the
actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
DDR2 SDRAM does not allow interrupting or truncating any WRITE
burst using BL = 4 operation. Once the BL = 4 WRITE command is
registered, it must be allowed to complete the entire WRITE burst
cycle. However, a WRITE (with auto precharge disabled) using BL
= 8 operation might be interrupted and truncated ONLY by another
WRITE burst as long as the interruption occurs on a 4-bit boundary,
due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst
BL = 8 operations may not to be interrupted or truncated with any
command except another WRITE command.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory; if the DM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
WRITE operation
Data for any WRITE burst may be followed by a subsequent READ
command. The number of clock cycles required to meet tWTR is
either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst
may be followed by a subsequent PRECHARGE command. tWR
must be met. tWR starts at the end of the data burst, regardless of
the data mask condition.
WRITE bursts are initiated with a WRITE command, as shown in
Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock
cycle [WL = RL - 1CK]. The starting column and bank addresses
are provided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the completion
of the burst.
During WRITE bursts, the first valid data-in element will be
registered on the first rising edge of DQS following the WRITE
command, and subsequent data elements will be registered on
successive edges of DQS. The LOW state on DQS between the
WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element
is known as the write postamble.
The time between the WRITE command and the first rising DQS
edge is WL ± tDQSS. Subsequent DQS positive rising edges are
timed, relative to the associated clock edge, as ± tDQSS. tDQSS is
specified with a relatively wide range (25 percent of one clock
cycle). All of the WRITE diagrams show the nominal case, and
17
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
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