W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 10 – ACTIVE COMMAND
DESELECT
The DESELECT function (CS# HIGH) prevents new commands
from being executed by the DDR2 SDRAM. The DDR2 SDRAM
is effectively deselected. Operations already in progress are not
affected. DESELECT is also referred to as COMMAND INHIBIT.
CK#
CK
NO OPERATION (NOP)
CKE
CS#
The NO OPERATION (NOP) command is used to instruct the
selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,
CAS#, and WE are HIGH). This prevents unwanted commands
from being registered during idle or wait states. Operations already
in progress are not affected.
RAS#
CAS#
WE#
LOAD MODE (LM)
The mode registers are loaded via inputs BA2–BA0, andA13–A0.
BA2–BA0 determine which mode register will be programmed.
See “Mode Register (MR)”. The LM command can only be issued
when all banks are idle, and a subsequent execute able command
cannot be issued until tMRD is met.
Row
ADDRESS
BANK ADDRESS
Bank
ACTIVATE COMMAND
The ACTIVATE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on the
BA2–BA0 inputs selects the bank, and the address inputs select
the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the
same bank.
DON’T CARE
ACTIVE OPERATION
A subsequent ACTIVATE command to a different row in the
same bank can only be issued after the previous active row has
been closed (precharged). The minimum time interval between
successive ACTIVATE commands to the same bank is defined
Before any READ or WRITE commands can be issued to a
bank within the DDR2 SDRAM, a row in that bank must be
opened (activated), even when additive latency is used. This is
accomplished via the ACTIVATE command, which selects both
the bank and the row to be activated.
by tRC
.
AsubsequentACTIVATE command to another bank can be issued
while the first bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between
successive ACTIVATE commands to different banks is defined by
After a row is opened with an ACTIVATE command, a READ or
WRITE command may be issued to that row, subject to the tRCD
specification. tRCD (MIN) should be divided by the clock period and
rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or
WRITE command can be entered. The same procedure is used
to convert other specification limits from time units to clock cycles.
For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock
(tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.
tRRD. This device has an additional requirement: tFAW. This requires
no more than four ACTIVATE commands may be issued in any
given tFAW (MIN) period.
15
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
