W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 11 – READ COMMAND
READ COMMAND
The READ command is used to initiate a burst read access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–i (where i = A9) selects
the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
CK#
CK
CKE
CS#
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying the
actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
RAS#
CAS#
READ OPERATION
WE#
READ bursts are initiated with a READ command. The starting
column and bank addresses are provided with the READ
command, and auto precharge is either enabled or disabled for
that burst access. If auto precharge is enabled, the row being
accessed is automatically precharged at the completion of the
burst. If auto precharge is disabled, the row will be left open after
the completion of the burst.
ADDRESS
Col
ENABLE
A10
AUTO PRECHARGE
BANK ADDRESS
DISABLE
Bank
During READ bursts, the valid data-out element from the starting
column address will be available READ latency (RL) clocks later.
RL is defined as the sum of AL and CL; RL = AL + CL. The value
forAL and CL are programmable via the MR and EMR commands,
respectively. Each subsequent data-out element will be valid
nominally at the next positive or negative clock edge (at the next
crossing of CK and CK#).
DON’T CARE
DQS/DQS# is driven by the DDR2 SDRAM along with output data.
The initial LOW state on DQS and HIGH state on DQS# is known
as the read preamble (tRPRE). The LOW state on DQS and HIGH
state on DQS# coincident with the last data-out element is known
as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have
been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with data from
a subsequent READ command to provide a continuous fl ow of
data. The first data element from the new burst follows the last
element of a completed burst. The new READ command should
be issued x cycles after the first READ command, where x equals
BL / 2 cycles.
DDR2 SDRAM does not allow interrupting or truncating of any
READ burst using BL = 4 operations. Once the BL = 4 READ
command is registered, it must be allowed to complete the entire
READ burst. However, a READ (with auto precharge disabled)
using BL = 8 operation may be interrupted and truncated only by
another READ burst as long as the interruption occurs on a 4-bit
boundary due to the 4n prefetch architecture of DDR2 SDRAM.
Data from any READ burst must be completed before a subsequent
WRITE burst is allowed.
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4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
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