W3H128M72E-XSBX / W3H128M72E-XNBX
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
BA1
BA0
A13
A12
A11
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
REFRESH
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
2
X
X
X
X
X
X
SELF-REFRESH Entry
L
X
X
H
H
H
H
SELF-REFRESH Exit
L
H
X
X
X
X
7
2
Single bank precharge
All banks PRECHARGE
Bank activate
H
H
H
H
H
H
BA
X
X
X
L
H
X
X
L
H
BA
Row Address
Column
Address
Column
Address
WRITE
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
BA
BA
BA
BA
L
H
L
2, 3
2, 3
2, 3
2, 3
Column
Address
Column
Address
WRITE with auto precharge
READ
Column
Address
Column
Address
H
H
Column
Address
Column
Address
READ with auto precharge
H
NO OPERATION
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT
POWER-DOWN entry
H
L
L
X
X
X
X
X
X
X
X
4
4
H
L
POWER-DOWN exit
H
NOTES:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
14
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
