W3H128M72E-XSBX / W3H128M72E-XNBX
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in
Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should
not be used as unknown operation or incompatibility with future
versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the requirement
that AL ≤ tRCD (MIN). A typical application using this feature would
set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is
held for the time of the AL before it is issued internally to the
DDR2 SDRAM device. RL is controlled by the sum of AL and CL;
RL = AL+CL. Write latency (WL) is equal to RL minus one clock;
WL = AL + CL - 1 x tCK
.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA2
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
Extended mode
register (Ex)
16 15 14 13 12 11 10
9
0
8
0
7
SRT
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
MRS
0
0
0
0
E7
0
SRT Enable
1X refresh rate (+85°C max junction temp.)
1
2X refresh rate (+85°C to +95°C junction temp.)
E15 E14
Mode Register Set
Mode register (MR)
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
12
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
