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W3H128M72E-400NBM 参数 Datasheet PDF下载

W3H128M72E-400NBM图片预览
型号: W3H128M72E-400NBM
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX72, 1.35ns, CMOS, PBGA208, BGA-208]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 31 页 / 1024 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
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W3H128M72E-XSBX / W3H128M72E-XNBX  
EXTENDED MODE REGISTER (EMR)  
The extended mode register controls functions beyond those  
controlled by the mode register; these additional functions are DLL  
enable/disable, output drive strength, on die termination (ODT),  
posted AL, off-chip driver impedance calibration (OCD), DQS#  
enable/disable, RDQS/RDQS# enable/disable, and output disable/  
enable. These functions are controlled via the bits shown in Figure  
7. The EMR is programmed via the LOAD MODE (LM) command  
and will retain the stored information until it is programmed again  
or the device loses power. Reprogramming the EMR will not alter  
the contents of the memory array, provided it is performed correctly.  
The EMR must be loaded when all banks are idle and no bursts  
are in progress, and the controller must wait the specied time  
tMRD before initiating any subsequent operation. Violating either  
of these requirements could result in an unspecied operation.  
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION  
BA2 BA1 BA0A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
Address Bus  
Extended Mode  
Register (Ex)  
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL  
out  
0
MRS  
0
E0  
DLL Enable  
E12 Outputs  
E6 E2 RTT (nominal)  
0
1
0
1
Enabled  
Disabled  
Enable (Normal)  
R
TT disabled  
75Ω  
0
0
1
1
0
1
0
1
Disable (Test/Debug)  
E11 RDQS Enable  
E1  
Output Drive Strength  
Full strength (18Ω target)  
150Ω  
0
1
No  
50Ω  
0
1
Yes  
Reduced strength (40Ω target)  
E10 DQS# Enable  
E5 E4 E3 Posted CAS# Additive Latency (AL)  
0
1
Enable  
Disable  
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
E9 E8 E7 OCD Operation1  
3
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD exit  
Reserved  
Reserved  
Reserved  
4
5
6
Reserved  
Enable OCD defaults  
E15 E14  
Mode Register Set  
Mode register set (MRS)  
0
1
0
1
0
0
1
1
Extended mode register (EMR)  
Extended mode register (EMRS2)  
Extended mode register (EMRS3)  
NOTES:  
1.  
During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before  
initialization is nished.  
10  
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX  
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com  
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