IS42S16100E, IC42S16100E
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding
to the new write command can be input at the point
new write command is executed. To prevent collision
between input and output data at the DQn pins during
this operation, the
output data must be masked using the U/LDQM pins. The
interval (tc c d ) between these commands must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
WRITE B0
COMMAND
U/LDQM
DQ
READ A0
HI-Z
DIN B0
D
IN B1
DIN B2
DIN B3
READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 2, 3, burstlength = 4
30
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
