IS42S16100E, IC42S16100E
Precharge
Read Cycle Interruption
The precharge command sets the bank selected by
pin A11 to the precharged state. This command can be
executed at a time tr a s following the execution of an active
command to the same bank. The selected bank goes to
the idle state at a time tr p following the execution of the
precharge command, and an active command can be
executed again for that bank.
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tr q l ) from the execution of the precharge
command to the completion of the burst output is the
clock cycle of CAS latency.
If pinA10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
CAS Latency
3
2
tr q l
3
2
CLK
tRQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
RQL
PRE 0
COMMAND
DQ
READ A0
DOUT A0
DOUT A1
DOUT A2
HI-Z
READ (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
