IS42S16100E, IC42S16100E
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delaytime(tw d l )fromtheprechargecommandtothepoint
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (td p l ) has elapsed. Therefore, the
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
CAS Latency
3
2
tw d l
0
0
This precharge command and burst write command must
beofthesamebank, otherwiseitisnotprechargeinterrupt
but only another bank precharge of dual bank operation.
td p l
1
1
CLK
tWDL=0
PRE 0
COMMAND
WRITE A0
DQM
DQ
DIN A0
DIN A1
D
IN A2
DIN A3
MASKED BY DQM
PRECHARGE (BANK 0)
WRITE (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
DPL
PRE 0
COMMAND
DQ
WRITE A0
DIN A0
D
IN A1
DIN A2
DIN A3
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS latency = 3, burstlength = 4
32
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
