IS42S16100E, IC42S16100E
Interval Between Read Command
A new command can be executed while a read cycle
is in progress, i.e., before that cycle completes. When
the second read command is executed, after the CAS
latency has elapsed, data corresponding to the new read
command is output in place of the data due to the previous
read command.
The interval between two read command (tc c d ) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
DQ
READ A0
READ B0
D
OUT A0
DOUT B0
D
OUT B1
DOUT B3
DOUT B2
t
CCD
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
Interval Between Write Command
Anew command can be executed while a write cycle is in
progress, i.e., beforethatcyclecompletes.Atthepointthe
second write command is executed, data corresponding
to the new write command can be input in place of the
data for the previous write command.
The interval between two write commands (tc c d ) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0 WRITE B0
DIN A0
D
IN B0
D
IN B1
D
IN B2
DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
28
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
