IS42S16100E, IC42S16100E
Interval Between Write and Read Commands
Anew read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
The interval (tc c d ) between command must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
CLK
tCCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
CCD
COMMAND
DQ
WRITE A0 READ B0
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
29
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
