IS42S16100E, IC42S16100E
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100E/IC42S16100E can output data
continuously from the burst start address (a) to location
a+255 during a read cycle in which the burst length is set
to full page. The IS42S16100E/IC42S16100E repeats the
operation starting at the 256th cycle with the data output
returning to location (a) and continuing with a+1, a+2, a+3,
etc. Aburst stop command must be executed to terminate
this cycle.Aprecharge command must be executed within
theACT to PRE command period (tr a s max.) following the
burst stop command.
After the period (tr b d ) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (tr b d ) is two clock cycle when the
CAS latency is two and three clock cycle when the CAS
latency is three.
CAS Latency
3
2
tr b d
3
2
CLK
tRBD
BST
COMMAND
DQ
READ A0
D
OUT A0
DOUT A0
D
OUT A1
D
OUT A2
DOUT A3
HI-Z
BURST STOP
READ (CA=A, BANK 0)
CAS latency = 2, burstlength = 4
CLK
t
RBD
BST
COMMAND
DQ
READ A0
D
OUT A0
D
OUT A0
D
OUT A2
D
OUT A3
D
OUT A1
HI-Z
READ (CA=A, BANK 0)
BURST STOP
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com
33
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
