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IC42S16100E-6TL 参数 Datasheet PDF下载

IC42S16100E-6TL图片预览
型号: IC42S16100E-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 81 页 / 1082 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S16100E, IC42S16100E  
Write Cycle (Full Page) Interruption Using  
the Burst Stop Command  
must be executed within the ACT to PRE command  
period (tr a s max.) following the burst stop command.  
After the period (tw b d ) required for burst data input to  
stop following the execution of the burst stop command  
has elapsed, the write cycle terminates. This period  
(tw b d ) is zero clock cycles, regardless of the CAS  
latency.  
The IS42S16100E/IC42S16100E can input data  
continuously from the burst start address (a) to location  
a+255 during a write cycle in which the burst length  
is set to full page. The IS42S16100E/IC42S16100E  
repeats the operation starting at the 256th cycle with  
data input returning to location (a) and continuing with  
a+1, a+2, a+3, etc. A burst stop command must be  
executed to terminate this cycle. A precharge command  
CLK  
t
WBD=0  
BST  
INVALID DATA  
tRP  
PRE 0  
COMMAND  
DQ  
WRITE A0  
DIN A0  
DIN A1  
DIN  
A
DIN A1  
DIN A2  
READ (CA=A, BANK 0)  
BURST STOP PRECHARGE (BANK 0)  
Don't Care  
Burst Data Interruption Using the U/LDQM  
Pins (Read Cycle)  
output control operates independently on a byte basis  
with the UDQM pin controlling upper byte output (pins  
DQ8-DQ15) and the LDQM pin controlling lower byte  
output (pins DQ0 to DQ7).  
Burst data output can be temporarily interrupted (masked)  
during a read cycle using the U/LDQM pins. Regardless of  
the CAS latency, two clock cycles (tq m d ) after one of the  
U/LDQM pins goes HIGH, the corresponding outputs go  
to the HIGH impedance state. Subsequently, the outputs  
are maintained in the high impedance state as long as  
that U/LDQM pin remains HIGH. When the U/LDQM pin  
goes LOW, output is resumed at a time tq m d later. This  
Since the U/LDQM pins control the device output buffers  
only, the read cycle continues internally and, in particular,  
incrementing of the internal burst counter continues.  
CLK  
COMMAND  
UDQM  
READ A0  
t
QMD=2  
LDQM  
DQ8-DQ15  
DQ0-DQ 7  
D
OUT A0  
D
OUT A2  
DOUT A3  
HI-Z  
HI-Z  
DOUT A0  
D
OUT A1  
HI-Z  
READ (CA=A, BANK 0)  
DATA MASK (LOWER BYTE)  
DATA MASK (UPPER BYTE)  
CAS latency = 2, burstlength = 4  
34  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. C  
01/22/08  
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