IS42S16100E, IC42S16100E
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
usedasthestartingaddress.First,thedatacorrespondingto
thisaddressisoutputinsynchronizationwiththeclocksignal
after the CAS latency period. Next, data corresponding to
anaddressgeneratedautomaticallybythedeviceisoutput
in synchronization with the clock signal.
isafullpageisanexception.Inthiscasetheoutputbuffers
must be set to the high impedance state by executing a
burst stop command.
Note that upper byte and lower byte output data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (tq m d ) is
fixed at two, regardless of the CAS latency setting, when
this function is used.
The output buffers go to the LOW impedance state CAS
latencyminusonecycleafterthereadcommand,andgoto
theHIGHimpedancestateautomaticallyafterthelastdata
is output. However, the case where the burst length
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
UDQM
READ A0
t
QMD=2
LDQM
DQ8-DQ15
DQ0-DQ 7
D
OUT A0
D
OUT A2
HI-Z
DOUT A3
HI-Z
HI-Z
DOUT A0
D
OUT A1
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
CAS latency = 3, burst length = 4
Burst Write
The write cycle is started by executing the command.
The address provided during write command execution
is used as the starting address, and at the same time,
data for this address is input in synchronization with the
clock signal.
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: td p l ) after the last data input is
required for the device to complete the write operation.
Note that the upper byte and lower byte input data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (td m d ) is
fixed at zero, regardless of the CAS latency setting, when
this function is used.
Next, data is input in other in synchronization with the
clock signal. During this operation, data is written to
addressgeneratedautomaticallybythedevice.Thiscycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
Inthiscasethewritecyclemustbeterminatedbyexecuting
The selected bank must be set to the active state before
executing this command.
CLK
COMMAND
DQ
WRITE
DIN
0
DIN
1
DIN
2
DIN 3
BURST LENGTH
CAS latency = 2,3, burst length = 4
Integrated Silicon Solution, Inc. — www.issi.com
25
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
