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HSP50110JI-52 参数 Datasheet PDF下载

HSP50110JI-52图片预览
型号: HSP50110JI-52
PDF下载: 下载PDF文件 查看货源
内容描述: 数字正交调谐器 [Digital Quadrature Tuner]
分类和应用: 电信集成电路
文件页数/大小: 24 页 / 202 K
品牌: INTERSIL [ Intersil ]
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HSP50110  
o
o
o
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AC Electrical Specifications Note 8, V = 5.0V ±5%, T = 0 to 70 C Commercial, T = -40 to 85 C Industrial (Continued)  
CC  
A
A
-52 (52.6MHz)  
PARAMETER  
SYMBOL  
NOTES  
MIN  
MAX  
UNITS  
ns  
CLK to IOUT9-0, QOUT9-0, DATARDY, LOTP, SSTRB, SPH4-0, HI/LO  
T
-
16  
16  
16  
-
8
-
DO  
WR High  
T
ns  
WRH  
WR Low  
T
-
ns  
WRL  
RD Low  
T
-
ns  
RDL  
RDO  
ROD  
RD LOW to Data Valid  
RD HIGH to Output Disable  
Output Enable  
WR to CLK  
T
T
15  
8
8
-
ns  
Note 8  
-
ns  
T
-
ns  
OE  
T
Note 9  
Note 8  
Note 8  
8
ns  
WC  
Output Disable Time  
Output Rise, Fall Time  
NOTES:  
T
-
8
3
ns  
OD  
T
-
ns  
RF  
7. AC tests performed with C = 40pF, I = 2mA, and I  
OL OH  
= -400µA. Input reference level for CLK is 2.0V, all other inputs 1.5V.  
L
Test V = 3.0V, V  
= 4.0V, V = 0V.  
IH  
IHC  
IL  
8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.  
9. Set time to ensure action initiated by WR or SERCLK will be seen by a particular clock.  
AC Test Load Circuit  
S1  
DUT  
C †  
L
±
IOH  
1.5V  
IOL  
EQUIVALENT CIRCUIT  
SWITCH S1 OPEN FOR I  
CCSB  
AND I  
CCOP  
Test head capacitance.  
3-251  
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