BBT3821
IEEE PHY XS REGISTERS (4.0 TO 4.25/4.0019’H)
Table 75. IEEE PHY XS CONTROL 1 REGISTER
MDIO REGISTER ADDRESS = 4.0 (4.0000’h)
BIT(S)
NAME
SETTING
DEFAULT
0’b
R/W
DESCRIPTION
3.0.15
1.0.15
4.0.15
Reset
1 = reset
R/W SC Writing 1 to this bit will reset the whole chip,
including the MDIO registers.
0 = reset done, normal
operation
4.0.14
PHY XS Loopback 1 = Enable loopback
0 = Normal operation
0’b
1’b
R/W
RO
Enable PHY XS loop back mode on all four lanes.
Operates at 10Gbps & above
3.0.13
4.0.13
Speed Select
1 = 10Gbps
4.0.12
4.0.11
Reserved
00’h
0’b
LOPOWER
Reserved
0 = Normal Power
R/W
No Low Power Mode, writes ignored
4.0.10:7
3.0.6
4.0.6
Speed Select
1 = 10Gbps
1’b
0’h
0’b
RO
RO
Operates at 10Gbps & above
Operates at 10Gbps
3.0.5:2
4.0.5:2
Speed Select
Reserved
0000 = 10Gbps
4.0.1:0
Table 76. IEEE PHY XS STATUS 1 REGISTER
MDIO REGISTER ADDRESS = 4.1 (4.0001’h)
BIT
4.1.15:8
4.1.7
NAME
Reserved
SETTING
DEFAULT
R/W
DESCRIPTION
00’h
0
Local Fault
Reserved
1 = PHY XS Local Fault
RO
Derived from Register 4.0008’h
4.1.6:3
4.1.2
0’h
(1)
(1)
Tx Link Up
1 = XGXS Tx Link Up
0 = XGXS Tx Link Down
1
RO LL
RO
‘Up’ means XAUI-side signal level is OK, Byte
Synch and Lane-Lane Alignment have all
occurred
4.1.1
4.1.0
LoPwrAble
Reserved
Low Power Ability
0
0
Device does not support a low power mode
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
Table 77. IEEE PHY XS STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
MDIO REGISTER ADDRESSES = 4.8 (4.0008’h)
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
4.8.15:14
Device present
10 = Device present
10’b
RO
When read as “10”, it indicates that a device is present at
this device address
4.8.13:12
4.8.11
Reserved
TX LocalFlt
1 = TX Local Fault; on Egress 0’b
channel
RO/
Lane Alignment or Byte Alignment not done, or Loss of
Signal. From Reg. 4.24
(1)
LH
4.8.10
4.8.9:0
RX LocalFlt
Reserved
1 = RX Local Fault; on Ingress 0’b
channel
RO/
PLL lock failure (lack of RFCP/N signal)
(1)
LH
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28)
46
INTERSIL [ Intersil ]
