BBT3821
Table 81. PHY XS CONTROL REGISTER 3 (Continued)
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
(1)
BIT
NAME
MF_CTRL
SETTING
DEFAULT
R/W
R/W
DESCRIPTION
4.49153.2:0
0 = BIST_ERR
000’b
Control the meaning of Multi-function pins MF[3:0] of
the 4 lanes in the device selected by MF_SEL above
(bit 12)
1 = LOS
2,3 = Reserved
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PHY XS XAUI_EN, see also Table 65.
Note (3): This state machine is implemented according toIEEE 802.3ae-2002 clause 48.
Table 82. PHY XS INTERNAL ERROR CODE REGISTER
MDIO REGISTER, ADDRESS = 4.49154 (4.C002’h)
(1)
BIT
4.49154.15:8
4.49154.7:0
NAME
Reserved
SETTING
DEFAULT
R/W
DESCRIPTION
(2)
PHY XS
ERROR
Desired Value
FE’h
R/W
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden to FE’h by PHY XS XAUI_EN, see Table 65 and Table 81.
Table 83. PHY XS INTERNAL IDLE CODE REGISTER
MDIO REGISTER ADDRESS = 4.49155 (4.C003’h)
(1)
BIT
4.49155.15:8
4.49155.7:0
NAME
Reserved
SETTING
DEFAULT
R/W
DESCRIPTION
PHY XS
XG_IDLE
Desired Value
07’h
R/W
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 84. PHY XS MISCELLANEOUS LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.49156 (4.C004’h)
BIT
4.49156.15:13
4.49156.12
4.49156.11
4.49156.10
4.49156.9
NAME
Reserved
Test LP
SLP_3
SETTING
DEFAULT
R/W
DESCRIPTION
(1)
1 = enable
0’b
R/W
Serial Host Test Loopback
(2)
(2)
(2)
(2)
1 = enable PHY XS
Network Loopback
0 = disable
0’b
0’b
0’b
0’b
R/W
Internal PHY XS Serial Loop Back Enable for each
individual lane. When high, it routes the internal
XAUI Serial output to the Serial input.
SLP_2
SLP_1
4.49156.8
SLP_0
4.49156.7:4
4.49156.3
Reserved
PLP_3
(2)
(2)
(2)
(2)
1 = enable System (“PCS”) 0’b
Parallel Loopback
R/W
PCS Parallel Loop Back Enable for each individual
lane. When high, it routes the XAUI Serial input to
the Serial output via the full PHY XS.
4.49156.2
PLP_2
0’b
0 = disable
4.49156.1
PLP_1
0’b
0’b
4.49156.0
PLP_0
Note (1): Loopback is from XAUI Serial I/P to Serial O/P. Recommended use for test purposes only; no retiming or pre-emphasis is performed
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
49
INTERSIL [ Intersil ]
