BBT3821
Table 68. PCS PARALLEL NETWORK LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 3.49156 (3.C004’h)
BIT
3.49156.15:4
3.49156.3
3.49156.2
3.49156.1
3.49156.0
NAME
Reserved
PLP_3
SETTING
DEFAULT
R/W
DESCRIPTION
(1)
1 = enable PCS Parallel 0’b
R/W
PCS Parallel Network Loop Back Enable for each
individual lane. When high, routes the CX4/LX4 Serial
input to the CX4/LX4 Serial output via the XGMII side
of the PCS.
(2)
Network loopback
(1)
(1)
(1)
PLP_2
0’b
0 = disable
PLP_1
0’b
0’b
PLP_0
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): Equivalent to a loopback at the XGMII input side of the PHY XS.
Table 69. PCS RECEIVE PATH TEST AND STATUS FLAGS
MDIO REGISTER ADDRESS = 3.49159 (3.C007’h)
BIT
3.49159.15:12
3.49159.11
3.49159.10
3.49159.9
3.49159.8
3.49159.7
NAME
Test Flags
EFIFO_3
EFIFO_2
EFIFO_1
EFIFO_0
Code_3
SETTING
DEFAULT
0’h
R/W
DESCRIPTION
Special test use only
ROLH
1 = EFIFO error in Lane 0’b
0 = no EFIFO error in
PCS Elasticity FIFO Overflow/Underflow Error
(1)
Detection
0’b
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
Lane
0’b
0’b
(1)
1 = 10b/8b Code error in 0’b
PCS 10b/8b Decoder Code Violation Detection
Lane
3.49159.6
3.49159.5
3.49159.4
3.49159.3:0
Code_2
0’b
0 = no 10b/8b Code error
Code_1
0’b
0’b
0’h
Code_0
Test Flags
Special test use only
Note (1): Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the
LASI register 1.9003’h (see Table 27)
Table 70. PMA/PCS OUTPUT CONTROL & TEST FUNCTION REGISTER
MDIO REGISTER ADDRESS = 3.49160 (3.C008’h)
BIT
3.49160.15:14
3.49160.13
3.49160.12:10
3.49160.9
NAME
Reserved
SETTING
Enable Lane 3 O/P
Enable Lane 2 O/P
Enable Lane 1 O/P
Enable Lane 0 O/P
DEFAULT
10’b
R/W
R/W
DESCRIPTION
Test Function, do not alter
ENA_3
1’b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
Reserved
ENA_2
010’b
1’b
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
3.49160.8:6
3.49160.5
Reserved
ENA_1
010’b
1’b
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
3.49160.12:10
3.49160.1
Reserved
ENA_0
010’b
1’b
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
3.49160.0
Reserved
0’b
43
INTERSIL [ Intersil ]
