BBT3821
Table 71. PCS/PHY XS HALF RATE CLOCK CONTROL REGISTER
MDIO REGISTER ADDRESSES = 3.49161 & 4.49161 ([3,4].C009’h)
BIT
NAME
Reserved
SETTING
DEFAULT
0’h
R/W
R/W
DESCRIPTION
3.49161.15:4
4.49161.15:4
3.49161.3
4.49161.3
HALF_RATE 3
HALF_RATE 2
HALF_RATE 1
HALF_RATE 0
1’b = half rate clock 0’b = full 0’b
rate clock
R/W
R/W
R/W
R/W
Lane 3 is running at half rate clock speed
Lane 2 is running at half rate clock speed
Lane 1 is running at half rate clock speed
Lane 0 is running at half rate clock speed
3.49161.2
4.49161.2
1’b = half rate clock 0’b = full 0’b
rate clock
3.49161.1
4.49161.1
1’b = half rate clock 0’b = full 0’b
rate clock
3.49161.0
4.49161.0
1’b = half rate clock 0’b = full 0’b
rate clock
Table 72. BIST CONTROL REGISTER
MDIO REGISTER ADDRESS = 3.49164 (3.C00C’h)
SETTING DEFAULT R/W
0’b R/W 1 = Enable BIST generator
(1)
BIT
NAME
DESCRIPTION
3.49164.15
BIST_EN
BIST generator
enable
0 = Disable BIST generator
3.49164.14:12
3.49164.11
Reserved
BIST_DIR
Select BIST data output
direction
0’b
0’h
R/W
R/W
1 = BIST to PCS (transmit path)
0 = BIST to XGXS (receive path)
3.49164.10:8
BIST_PAT
Select BIST
000 = CRPAT
(4)
generator data pattern
001 = CJPAT
010 = PRBS23 with 9 /K/s as IPG
(2)
011 = Short PRBS23 pattern
(3)
100 = Jumbo Ethernet packet
Other = reserved
3.49164.7
BIST_DET
BIST checker enable
0’b
R/W
1 = Enable BIST checker
0 = Disable BIST checker
3.49164.6:4
3.49164.3
Reserved
BIST_SRC
Select BIST data checker 0’b
input source
R/W
R/W
0 = PCS to BIST (receive path)
1 = XGXS to BIST (transmit path)
3.49164.2:0
BIST_CHK
Select BIST
0’h
000 = CRPAT
(5)
checker data pattern
001 = CJPAT
010 = PRBS23 with /K/’s as IPG
(2)
011 = Short PRBS23 pattern
(3)
100 = Jumbo Ethernet packet
Other = reserved
Note (1): See “BIST Operation” on page 53 for a description of these tests and patterns.
23
Note (2): This Short pattern is the first 13458 Bytes of the full PRBS 2 -1 Byte pattern, and also has 9 /K/ per lane as IPG
Note (3): This pattern is an /S/, preamble, the ‘Short PRBS23’ pattern, one /T/, and 9 /K/s, repeated.
Note (4): A Soft Reset is required to activate the newly selected pattern.
Note (5): The checker expects at least one /K/ on each lane between pattern repeats
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INTERSIL [ Intersil ]
