BBT3821
Table 80. PHY XS CONTROL REGISTER 2 (Continued)
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
(1)
BIT
NAME
PHY XS
PCS_SYNC_EN
SETTING
DEFAULT
R/W
R/W
DESCRIPTION
(2)
(3)
4.49152.4
0 = disable
0’b
Enable 8b/10b PCS coding synchronized state machine to
control the byte alignment (IEEE ‘code-group alignment’) of
the high speed de-serializer
(5)
1 = enable
4.49152.3
4.49152.2
4.49152.1
PHY XS IDLE_D_EN 1 = enable
0 = disable
1’b
1’b
1’b
R/W
R/W
R/W
Enables IDLE vs. NON-IDLE detection for lane alignment.
Overridden by PHY XS XAUI_EN, see Table 88
PHY XS ELST_EN
1 = enable
0 = disable
Enable the elastic function of the PHY XS receiver buffer
(2)
PHY XS
A_ALIGN_DIS
1 = disable
0 = enable
PHY XS Receiver aligns data on incoming “/A/” characters
(K28.3). If disabled (default), receiver aligns data on IDLE to
non-IDLE transitions (if bit 3 set). Overridden by PHY XS
XAUI_EN, see Table 81
4.49152.0
PHY XS CAL_EN
1 = enable
0 = disable
1’b
R/W
Enable de-skew calculator of PHY XS receiver Align FIFO
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PHY XS XAUI_EN, see Table 81 and Table 65.
Note (3): These state machines are implemented according to 802.3ae-2002 clause 48.
Note (4): If the RCLKMODE bits are set to 10’b, the internal XGMII clock from the PHY XS to the PCS is set to the recovered clock. If the PHY XS Clock PSYNC bit is set (the
default), the recovered clock from Lane 0 is used for all four lanes, if cleared, or if the RCLKMODE bits are set to 01’b or 00’b, each lane uses its own recovered clock.
If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost, or repeated).
Note (5): This bit name reflects the “embedded” PCS function within an XGXS, see IEEE 802.3 Clause 47.2.1.
Table 81. PHY XS CONTROL REGISTER 3
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
(1)
BIT
NAME
SETTING
DEFAULT
R/W
R/W
DESCRIPTION
PHY XS DC Offset Disable
4.49153.15
4.49153.14:13
4.49153.12
PHY XS DC_O_DIS 1 = Disable, 0 = normal 0’b
Reserved
MF_SEL
Select source of signals 0’b
for four MF pins
R/W
R/W
R/W
1 = Select signals from PMA/PCS
to be output on MF pins
0 = Select signals from PHY
XGXS to be output on MF pins
4.49153.11
PHY XS XAUI_EN
PHY_LOS_TH
1 = enable
0 = disable
1’b
Enables all XAUI features per 802.3ae-2002. It is
equivalent to setting the configuration bits listed in
Table 65 (but does not change the actual value of the
corresponding MDIO registers’ bits).
4.49153.10:8
0’h = 160mV
1’h = 240mV
2’h = 200mV
3’h = 120mV
000’b
Set the threshold voltage for the Loss Of Signal
(LOS) detection circuit in PHY XS. Nominal levels are
listed for each control value. Note that the differential
peak-to-peak value is twice that listed
p-p
p-p
p-p
p-p
4’h = 80mV
p-p
else = 160mV
p-p
4.49153.7
4.49153.6
Reserved
(3)
PHY XS
AKR_SM_EN
1 = enable random A/K/R 0’b
R/W
R/W
Enable pseudo- random A/K/R in Inter Packet Gap
(2)
0 = /K/ only
(IPG) on transmitter side (vs. /K/ only)
4.49153.5
PHY XS TRANS_EN 1 = enable
0 = disable
0’b
This bit enables the transceiver to translate an “IDLE”
pattern in the internal FIFOs (matching the value of
register 4.C003’h) to and from the XAUI IDLE /K/
comma character or /A/, /K/ & /R/ characters.
(2)
Overridden by PHY XS
XAUI_EN, see Table 65
4.49153.4
4.49153.3
Reserved
PHY XS TX_SDR
PHY XS receive
data rate
0’b
R/W
1 = PHY XS takes data from PCS at half speed
0 = PHY XS takes data from PCS at full speed
48
INTERSIL [ Intersil ]
