Package Mechanical Specifications and Pin Information
Signal Name
Type
Description
IERR# (Internal Error) is asserted by a processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until
the assertion of RESET#, BINIT#, or INIT#.
IERR#
O
IGNNE# (Ignore Numeric Error) is asserted to force the processor
to ignore a numeric error and continue to execute non-control
floating-point instructions. If IGNNE# is de-asserted, the
processor generates an exception on a non-control floating-point
instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register-0 (CR0)
is set.
IGNNE#
I
I
I
IGNNE# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output write
instruction, it must be valid along with the TRDY# assertion of
the corresponding Input/Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at
the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal.
However, to ensure recognition of this signal following an
Input/Output Write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus
transaction. INIT# must connect the appropriate pins of both FSB
agents.
INIT#
If INIT# is sampled active on the active to inactive transition of
RESET#, the processor reverses its FSB data and address signals
internally to ease motherboard layout for systems where the
chipset is on the other side of the motherboard.
D [63:0] => D [0:63]
A [31:3] => A [3:31]
DINV [3:0]# is also reversed.
LINT [1:0] (Local APIC Interrupt) must connect the appropriate
pins of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
LINT [1:0]
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as
NMI/INTR or LINT [1:0]. Because the APIC is enabled by default
after Reset, operation of these pins as LINT [1:0] is the default
configuration.
Datasheet
45
INTEL [ INTEL ]
