Package Mechanical Specifications and Pin Information
Signal Name
Type
Description
BPM [0]#
BPM [1]#
BPM [2]#
O
I/O
O
BPM [3:0]# (Breakpoint Monitor) are breakpoint and
performance monitor signals. They are outputs from the
processor which indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. BPM [3:0]# should connect the appropriate pins of
all FSB agents. This includes debug or performance monitoring
tools.
BPM [3]#
I/O
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the FSB. It must connect the appropriate pins of both FSB
agents. Observing BPRI# active (as asserted by the priority
agent) causes the other agent to stop issuing new requests,
unless such requests are part of an ongoing locked operation.
The priority agent keeps BPRI# asserted until all of its requests
are completed then releases the bus by de-asserting BPRI#.
BPRI#
I
BR0# is used by the processor to request the bus. The arbitration
is done between the processor (Symmetric Agent) and Intel
945GSE (High Priority Agent).
BR0#
I/O
BSEL [2:0] (Bus Select) are used to select the processor input
clock frequency. Table 4 defines the possible combinations of the
signals and the frequency associated with each combination. The
required frequency is determined by the processor, chipset and
clock synthesizer. All agents must operate at the same frequency.
For Intel® Atom™ processor N270, the BSEL is fixed to operat at
133-MHz BCLK frequency.
BSEL [2:0]
COMP [3:0]
O
COMP [3:0] must be terminated on the system board using
precision (1% tolerance) resistors.
PWR
D [63:0]# (Data) are the data signals. These signals provide a
64-bit data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY#
to indicate a valid data transfer.
D [63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D [63:0]# are latched off the
falling edge of both DSTBP [3:0]# and DSTBN [3:0]#. Each
group of 16 data signals correspond to a pair of one DSTBP# and
one DSTBN#. The following table shows the grouping of data
signals to data strobes and DINV#.
Quad-Pumped Signal
Groups Data Group
DSTBN#/DSTBP#
DINV#
D [63:0]#
I/O
D [15:0]#
D [31:16]#
D [47:32]#
D [63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
42
Datasheet
INTEL [ INTEL ]
