Package Mechanical Specifications and Pin Information
Signal Name
Type
Description
Asserting the RESET# signal resets the processor to a known
state and invalidates its internal caches without writing back any
of their contents. For a power-on Reset, RESET# must stay active
for at least two milliseconds after VCC and BCLK have reached
their proper specifications. On observing active RESET#, both
FSB agents will de-assert their outputs within two clocks. All
processor straps must be valid within the specified setup time
before RESET# is de-asserted.
RESET#
I
Please contact your Intel representative for more implementation
details.
RS [2:0]# (Response Status) are driven by the response agent
(the agent responsible for completion of the current transaction),
and must connect the appropriate pins of both FSB agents.
RS [2:0]#
RSVD
I
Reserved All other RSVD signals can be left as No Connects.
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts.
The processor will recognize only assertion of the RESET# signal,
de-assertion of SLP#, and removal of the BCLK input while in
SLP#
I
Sleep state. If SLP# is de-asserted, the processor exits Sleep
state and returns to Stop-Grant state, restarting its internal clock
signals to the bus and processor core units. If DPSLP# is asserted
while in the Sleep state, the processor will exit the Sleep state
and transition to the Deep Sleep state.
SMI# (System Management Interrupt) is asserted
asynchronously by system logic. On accepting a System
Management Interrupt, the processor saves the current state and
SMI#
I
enters System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program
execution from the SMM handler. If SMI# is asserted during the
de-assertion of RESET# the processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal
clock signals to all processor core units except the FSB and APIC
units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is
de-asserted, the processor restarts its internal clock to all units
and resumes execution. The assertion of STPCLK# has no effect
on the bus clock; STPCLK# is an asynchronous input.
STPCLK#
I
TCK (Test Clock) provides the clock input for the processor Test
Bus (also known as the Test Access Port). Please contact your
Intel representative for more implementation details.
TCK
TDI
I
I
TDI (Test Data In) transfers serial test data into the processor.
TDI provides the serial input needed for JTAG specification
support. Please contact your Intel representative for more
implementation details.
Datasheet
47
INTEL [ INTEL ]
